Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and non-volatile flash) memory.
Flash memory devices typically use a one-transistor memory cell that may allow for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the memory cells, through programming of a charge storage structure such as floating gates, trapping layers or other physical phenomena, may determine the data state of each cell.
The memory cells may be arranged in strings of memory cells where each string may be coupled to a source. Groups of strings of memory cells (e.g., memory blocks) may all be coupled to a common source.
FIG. 1 illustrates a schematic diagram of a typical string 100 of memory cells. The string 100 can include a source select gate transistor 120 that may include an n-channel transistor coupled between one of the memory cells 112 at one end of the string 100 and a common source 126. The common source 126 may comprise, for example, a commonly doped semiconductor material and/or other conductive material. At the other end of the string 100, a drain select gate transistor 130 may include an n-channel transistor coupled between one of the memory cells 112 and a data line (e.g., bit line) 134.
Each of the memory cells 112 may comprise, for example, a floating gate transistor or, alternatively, a charge trap transistor and may include a single level charge storage device or a multilevel charge storage device. The memory cells 112, the source select gate transistor 120, and the drain select gate transistor 130 can be controlled by signals on their respective control gates, the signals being provided on access lines (e.g., word lines) WL0-WL15 and select lines SOS and SOD. In one embodiment, the control gates of memory cells in a row of memory cells can form part of an access line.
The source select gate transistor 120 receives a control signal SGS that controls the source select gate transistor 120 to substantially control conduction between the string 100 and the common source 126. The drain select gate transistor 130 receives a control signal SOD that controls the drain select gate transistor 130, so that the drain select gate transistor 130 can be used to select or deselect the string 100.
The string 100 can be one of multiple strings of memory cells 112 in a block of memory cells in a memory device, such as a NAND-architecture flash memory device. Each string 100 of memory cells 112 may be formed in a three-dimensional (3D) manner such that the memory cells 112 and select gate transistors 120, 130 at least partially encircle a semiconductor channel.
As memory manufacturers move from a typical two dimensional (2D) NAND structure to a 3D NAND structure, at least the select gate drain transistors have shown a tendency towards greater current leakage. The bodies of select gate drain transistors of the 3D NAND are typically made of a polysilicon and have a tendency towards greater current leakage than the 2D NAND select gate transistors, the bodies of which are typically made of single crystal silicon.
Current leakage through the select gate drain transistors can cause problems with both programming and reading operations of the memory cells of a 3D NAND device. For example, during a program or read operation, electrons can penetrate into the channels of the unselected memory cell strings. Since a number of control gates of strings of memory cells can be connected in a row, the program or read voltage used to bias a control gate of a selected memory cell may be connected to the control gates of a number of unselected memory cells. Thus, even though the data line is typically inhibited to the unselected memory cell strings, any select gate drain current leakage may cause some of the unselected memory cells to be inadvertently programmed or a selected memory cell being read to be read incorrectly.